Vhdl Port Map Assignment Europe

The below is not a valid answer, since it does not adhere to the VHDL standard. This "answer" is however kept here, and not deleted, since it shows what construction to avoid for tool compliance, since some tools apparently accept this non-standard compliant VHDL code.

Example of port mapping without association of all scalar subelement, which is accepted by Altera Quartus II and Mentor ModelSim in some cases, but is also likely to result in warning or error:

So, as David Koontzs point out in the comment, the VHDL standard (IEEE Std 1076-2008) section "6.5.7 Association lists" describes:

... every scalar subelement of the explicitly declared interface object shall be associated exactly once with an actual (or subelement thereof) in the same association list, and all such associations shall appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object shall identify the formal with a locally static name.

So it is not valid to only associate some of the scalar subelements, since the standard says "every scalar subelement", and can't be used for the remaining scalar subelements, since the standard says "Each association element that associates a slice ... of an interface object shall identify the formal with a locally static name.".

Components and Port Maps

The example above shows the previously defined design entity AOI being used as a component within another, higher level design entity MUX2I, to create a design hierarchy with two levels. The design entity MUX2I also contains a second component, named INV. In order to write the VHDL for this circuit, we need to cover two new concepts: component instantiation (placing the INV and AOI inside another higher-level design, MUX2I) and port mapping (connecting up the two components to each other and to the primary ports of MUX2I). In VHDL, this is how we can model PCBs assembled from individual chips, for example.


The two component declarations (for INV and AOI) must match the corresponding entity declarations exactly with respect to the names, order and types of the ports. We've already seen enough of the AOI gate, let's see how closely the component and entity declarations match for the INV design entity.

entity INV is port (A: in STD_LOGIC; F: out STD_LOGIC);end INV;
component INV port (A: in STD_LOGIC; F: out STD_LOGIC);end component;

The two component declarations (for INV and AOI) appear in the architecture declarative part (that's a VHDL technical term that means that the component declarations are coded before the begin).

library IEEE;use IEEE.STD_LOGIC_1164.all;entity MUX2I is port (SEL, A, B: in STD_LOGIC; F : out STD_LOGIC);end;architecture STRUCTURE of MUX2I iscomponent INV port (A: in STD_LOGIC; F: out STD_LOGIC);end component;component AOI port (A, B, C, D: in STD_LOGIC; F : out STD_LOGIC);end component;signal SELB: STD_LOGIC;begin G1: INV port map (SEL, SELB); G2: AOI port map (SEL, A, SELB, B, F);end;


The architecture STRUCTURE of MUX2I makes instances of INV and AOI through the component instantiations at the bottom of the architecture (labelled G1 and G2). The component names (INV and AOI) are references to design entities defined elsewhere. The instance labels (G1 and G2) identify two specific instances of the components, and are mandatory.

Port Maps

The ports in a component declaration must usually match the ports in the entity declaration one-for-one. The component declaration defines the names, order, mode and types of the ports to be used when the component is instanced in the architecture body. Instancing a component implies making a local copy of the corresponding design entity - a component is declared once within any architecture, but may be instanced any number of times. In this example, there is just one instance of the components AOI and INV.


Signals in an architecture are associated with ports on a component using a port map. In effect, a port map makes an electrical connection between “pieces of wire” in an architecture (signals) and pins on a component (ports). The same signal may be associated with several ports - this is the way to define interconnections between components.

In our MUX2I example, the signal SELB is associated with the F port of the INV instance and the C port of the AOI instance.

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